(1) Field of the Invention
This invention relates to a semiconductor memory and, more particularly, to a semiconductor memory with a plurality of memory cells arranged in row and column directions like a matrix and connected between complementary bit lines.
(2) Description of the Related Art
FIG. 5 is a circuit diagram showing an example of memory cells included in static random access memories (SRAMs).
A memory cell 700 in an SRAM includes n-channel metal oxide semiconductor (MOS) field effect transistors (NMOSes) 701 and 702 and inverters 703 and 704 between complementary bit lines BL and /BL. One input-output terminal of the NMOS 701 is connected to the bit line BL and one input-output terminal of the NMOS 702 is connected to the bit line /BL. The other input-output terminal of the NMOS 701 is connected to an input terminal of the inverter 703 and the other input-output terminal of the NMOS 702 is connected to an output terminal of the inverter 703. The other input-output terminal of the NMOS 702 is connected to an input terminal of the inverter 704 and the other input-output terminal of the NMOS 701 is connected to an output terminal of the inverter 704. A common word line WL is connected to gates of the NMOSes 701 and 702.
FIGS. 6A and 6B are views showing potential levels at the time of a conventional SRAM being written. FIG. 6A is a, view showing the potential levels of the word line and the complementary bit lines. FIG. 6B is a view showing the potential levels of the word line and nodes c and cx shown in FIG. 5.
It is assumed that an SRAM is written. Usually the potential Vb1 of one (the bit line BL in FIG. 6A, for example) of the complementary bit lines BL and /BL is decreased from a power supply voltage (VDD) level to a ground (VSS) level and the potential Vb2 of the other (the bit line /BL in FIG. 6A) is kept at the VDD level. By doing so, a great potential difference arises between the bit lines BL and /BL to which the memory cell is connected. In addition, the word line WL is activated (its potential Vw is increased to the VDD level). As shown in FIG. 6B, the potential Vc of the node c and the potential Vcx of the node cx are inverted to write data into this memory cell.
In this case, however, the potential Vb2 of the bit line /BL which must be kept at the VDD level may drop with the change in the potential Vb1 of the bit line BL from the VDD level to the VSS level due to, for example, coupling capacitance 705 between the complementary bit lines BL and /BL. If the potential Vb2 of the bit line /BL drops and a great potential difference does not arise between the complementary bit lines BL and /BL, there may be a delay in an inversion of memory cell data or in the worst case the data cannot be written into the memory cell.
Conventionally, the following semiconductor memory has been known as a device which can solve this problem.
FIG. 7 is a circuit diagram of a conventional semiconductor memory.
A semiconductor memory 800 includes a plurality of memory cells 801 which are arranged in row and column directions like a matrix and which are connected between complementary bit lines BL and /BL, a column selection circuit 802, data bus lines 803a and 803b, a precharge circuit 804, a sense amplifier 805, and a write amplifier 806. In FIG. 7, word lines WL connected to the plurality of memory cells 801 are not shown.
The column selection circuit 802 includes an NMOS 802a and a p-channel MOS field effect transistor (PMOS) 802b which connect the data bus line 803a to one bit line BL of the complementary bit lines in response to a column selection signal (not shown) and a PMOS 802c and an NMOS 802d which connect the data bus line 803b to the other bit line /BL in response to the column selection signal.
The precharge circuit 804 includes PMOSes 804a, 804b, and 804c. The precharge circuit 804 precharges the data bus lines 803a and 803b to a VDD level in response to a precharge/equalize control signal inputted to gates of the PMOSes 804a, 804b, and 804c to make the potential of the data bus lines 803a and 803b equal.
At read operation time, the sense amplifier 805 detects and amplifies a difference in potential between the data bus lines 803a and 803b to read out data stored in a memory cell 801 selected.
The write amplifier 806 includes PMOSes 806a and 806b, NMOSes 806c and 806d, and inverters 806e, 806f, 806g, and 806h. When complementary data to be written (data to be written and /data to be written) is inputted, the potential of the data bus lines 803a and 803b is set to a VDD or VSS level to write the data into a memory cell 801.
In the semiconductor memory 800 having the above-mentioned structure, the bit line BL is connected to the data bus line 803a when both the NMOS 802a and the PMOS 802b turn on. The bit line /BL is connected to the data bus line 803b when both the PMOS 802c and the NMOS 802d turn on. Accordingly, by decreasing the potential of, for example, the data bus line 803a and increasing the potential of the data bus line 803b to the VDD level, it is possible to restore, via the PMOS 802c, the potential level of the bit line /BL which otherwise would have dropped due to coupling capacitance.
With the conventional semiconductor memory 800 shown in FIG. 7, however, the column selection circuit 802 connects the bit line BL and the data bus line 803a by turning on both the NMOS 802a and the PMOS 802b and connects the bit line /BL and the data bus line 803b by turning on both the PMOS 802c and the NMOS 802d, in response to a column selection signal (not shown). Accordingly, the number of transistors connected to the data bus lines 803a and 803b increases. In addition, the write amplifier 806 is connected to the data bus lines 803a and 803b. As a result, the load on each data bus line significantly increases. This greatly interferes with the driving of the bit lines BL and /BL and the data bus lines 803a and 803b when data is read out from a memory cell 801. Moreover, this may lead to a decrease in the operating speed of the sense amplifier 805. Therefore, read operation is not performed properly or the operating speed of the sense amplifier 805 decreases to stably perform read operation.
The following semiconductor memory in which read data bus lines are kept separate from write data bus lines has been known as a device which can solve these problems.
FIG. 8 is a circuit diagram of another conventional semiconductor memory.
A semiconductor memory 900 includes a plurality of memory cells 901 which are arranged in row and column directions like an array and which are connected between complementary bit lines BL and /BL, a bit line voltage boosting circuit section 902, a column selection circuit 903, write data bus lines 904a and 904b, read data bus lines 905a and 905b, a precharge circuit 906, a sense amplifier 907, and a write amplifier 908.
The bit line voltage boosting circuit section 902 includes PMOSes 902a and 902b. One input-output terminal of the PMOS 902a is connected to the bit line BL, a gate of the PMOS 902a is connected to the bit line /BL, and the other input-output terminal of the PMOS 902a is connected to a VDD terminal. One input-output terminal of the PMOS 902b is connected to the bit line /BL, a gate of the PMOS 902b is connected to the bit line BL, and the other input-output terminal of the PMOS 902b is connected to the VDD terminal.
The column selection circuit 903 includes NMOSes 903a and 903c and PMOSes 903b and 903d. The NMOS 903a connects the write data bus line 904a to the bit line BL of the pair of complementary bit lines in response to a column selection signal (not shown) inputted to its gate. The PMOS 903b connects the read data bus line 905a to the bit line BL in response to a column selection signal (not shown) inputted to its gate. The NMOS 903c connects the write data bus line 904b to the bit line /BL in response to the column selection signal inputted to its gate. The PMOS 903d connects the read data bus line 905b to the bit line /BL in response to the column selection signal inputted to its gate.
The precharge circuit 906 includes PMOSes 906a, 906b, and 906c. In response to a precharge/equalize control signal inputted to their gates, the precharge circuit 906 precharges the read data bus lines 905a and 905b to a VDD level and makes the potential of the read data bus lines 905a and 905b equal.
At read operation time, the sense amplifier 907 detects and amplifies a difference in potential between the read data bus lines 905a and 905b to read out data stored in a memory cell 901 selected.
The structure of the write amplifier 908 is the same as that of the write amplifier 806 shown in FIG. 7. When data to be written and /data to be written are inputted, the potential of the write data bus lines 904a and 904b is set to a VDD or VSS level to write the data into a memory cell 901.
In the semiconductor memory 900 having the above-mentioned structure, the bit line BL and the write data bus line 904a are connected only via the NMOS 903a and the bit line /BL and the write data bus line 904b are connected only via the NMOS 903c. There is no problem about the operation of decreasing the potential of one of the pair of bit lines. Unlike the semiconductor memory 800 shown in FIG. 7, however, it is impossible to restore the potential of the other which has dropped, as shown in FIG. 6, due to coupling capacitance to the VDD level. Accordingly, the semiconductor memory 900 includes the PMOSes 902a and 902b between the bit lines BL and /BL, being a pair of complementary bit lines. As a result, when the potential of, for example, the bit line BL is decreased to the VSS level, the PMOS 902b connected to the bit line /BL turns on and the potential of the bit line /BL can be restored to the VDD level. In addition, the read data bus lines are kept separate from the write data bus lines, so the load on each data bus line does not increase.
Conventionally, techniques for preventing data stored in a memory cell between bit lines which are not selected and which are next to selected bit lines from being lost by the influence of coupling capacitance at write operation time have been known. In Japanese Unexamined Patent Publication No. 10-112185 (paragraphs [0044]–[0049] and FIGS. 1 and 4), for example, a semiconductor memory in which a write precharge circuit for precharging, before write operation, a bit line, inputting a write precharge signal, and keeping the voltage of complementary bit lines high for a predetermined period of time is connected to each bit line is disclosed.
With the conventional semiconductor memory 900 shown in FIG. 8, however, the PMOSes 902a and 902b for restoring potential which has dropped due to coupling capacitance at write time must be located for each bit line. This leads to an increase in the area of the device.
Moreover, with the conventional semiconductor memory disclosed in, for example, Japanese Unexamined Patent Publication No. 10-112185 (paragraphs [0044]–[0049] and FIGS. 1 and 4), the write precharge circuit for keeping the voltage of complementary bit lines high for a predetermined period of time is connected to each bit line. As a result, the area of the device increases.